datasheet networking clock source ICS650-07C idt? / ics? networking clock source 1 ICS650-07C rev d 102709 description the ICS650-07C is a low cost, low jitter, high performance clock synthesizer for networking applications. using analog phase-locked loop (pll) techniques, the device accepts a 12.5 mhz or 25.00 mhz clock or fundamental mode crystal input to produce multiple output clocks for networking chips, pci devices, sdram, and asics. the ICS650-07C outputs all have 0 ppm synthesis error. see the mk74cb214, ics551, and ics552-01 for non-pll buffer devices which produce multiple low-skew copies of these output clocks. see the ics570, ics9112-16/17/18 for zero delay buffers that can synchronize outputs and other needed clocks. features ? packaged in 20-pin tiny ssop (qsop) ? pb (lead) free package ? 12.5 mhz or 25.00 mhz fundamental crystal or clock input ? six output clocks with selectable frequencies ? sdram frequencies of 67, 83, 100, and 133 mhz ? buffered crystal reference output ? zero ppm synthesis error in all clocks ? ideal for pmc-sierra?s atm switch chips ? full cmos output swing with 25 ma output drive capability at ttl levels ? advanced, low power, sub-micron cmos process ? 3.0 v to 5.5 v operating voltage block diagram clock synthesis and control circuitry clkc1 clkb1 12.5 mhz or 25.00 mhz crystal or clock clkb2 clkc2 oe (all outputs) refout clock buffer/ crystal oscillator x1/iclk x2 acs1, 0 bcs1, 0 ccs vdd 2 2 gnd 2 2 optional crystal capac itors are shown and may be required for tuning of initial accuracy clka1 clka2 /2 /2
ICS650-07C networking clock sour ce clock synthesizer idt? / ics? networking clock source 2 ICS650-07C rev d 102709 pin assignment pin descriptions 13 4 12 5 11 acs1 8 9 10 vdd clkc2 clka2 ccs clkb2 dc 17 16 clkb1 3 x1/iclk vdd clka1 18 refout 1 acs0 x2 bcs0 20 bcs1 19 14 2 7 gnd clkc1 oe gnd 15 6 20 pin (150 mil) ssop pin name pin type description 1 acs0 tri-level input a clock select 0. selects outputs on clka1 and clka2. see table below. 2 x2 xo crystal connection. connect to a cryst al or leave unconnected for clock input. 3 x1/iclk xi crystal connection. connect to fundamental crystal or clock input. 4 vdd power connect to 3.3 v or 5 v. must be same value as other vdd. 5 acs1 input a clock select 1. selects outputs on clka1 and clka2. internal pull-up resistor. see table below. 6 gnd power connect to ground. 7 clkc1 output clock c output 1. depends on setting of ccs per table below. 8 clkc2 output clock c output 2. depends on setting of ccs per table below. same as clkc1. 9 clkb2 output clock b output 2. depends on setting of bcs1, 0 per table below. 10 clkb1 output clock b output 1. depends on setting of bcs1, 0 per table below. 11 ccs tri-level input clock c select pin. select s outputs on clkc1 and clkc2 per table below. 12 dc ? don?t connect. do not connect anything to this pin. 13 clka2 output clock a output 2. depends on setting of acs1, 0 per table below. 14 gnd power connect to ground. 15 oe input output enable. tri-states all outputs when low. internal pull-up resistor. 16 vdd power connect to vdd. must be same value as other vdd. 17 clka1 output clock a output 1. depends on setting of acs1, 0 per table below. 18 refout output buffered reference clock output. same frequency as crystal or clock input. 19 bcs0 tri-level input b clock select 0. selects outputs on clkb1 and clkb2. see table below. 20 bcs1 input b clock select 1. selects outputs on clkb1 and clkb2. see table below.
ICS650-07C networking clock sour ce clock synthesizer idt? / ics? networking clock source 3 ICS650-07C rev d 102709 for a 25 mhz fundamental crystal or cl ock input, use the following tables: a clocks select table (mhz) c clocks select table (mhz) 0 = connect directly to ground 1 = connect directly to vdd m = leave unconnected (automatically self biases to vdd/2) b clocks select table (mhz) refout = 25 mhz acs1 acs0 clka1 clka2 0 0 100 off (low) 0 m test test 01 75 off (low) 1 0 33.3333 16.6667 1 m test test 1 1 66.6667 33.3333 ccs clkc1 clkc2 0 125 125 m test test 175 75 bcs1 bcs0 clkb1 clkb2 0 0 test test 0 m 66.6667 33.3333 0 1 100 50 1 0 83.3333 41.6667 1 m test test 1 1 133.3333 66.6667
ICS650-07C networking clock sour ce clock synthesizer idt? / ics? networking clock source 4 ICS650-07C rev d 102709 for a 12.5 mhz crystal or clock input, use the following tables: a clocks select table (mhz) c clocks select table (mhz) 0 = connect directly to ground 1 = connect directly to vdd m = leave unconnected (automatically self biases to vdd/2) b clocks select table (mhz) refout = 12.5 mhz acs1 acs0 clka1 clka2 00 50 off (low) 0 m test test 0 1 37.5 off (low) 1 0 16.6667 8.3333 1 m test test 1 1 33.3333 16.6667 ccs clkc1 clkc2 0 62.5 62.5 m test test 1 37.5 37.5 bcs1 bcs0 clkb1 clkb2 0 0 test test 0 m 33.3333 16.6667 01 50 25 1 0 41.66667 20.8333 1 m test test 1 1 66.6667 33.3333
ICS650-07C networking clock sour ce clock synthesizer idt? / ics? networking clock source 5 ICS650-07C rev d 102709 external components the ICS650-07C requires a minimum number of external components for proper operation. decoupling capacitor decoupling capacitors of 0.01f must be connected between each vdd and gnd (pins 4 and 6, pins 16 and 14), as close to the device as possible. for optimum device performance, the decoupling capacitor should be mounted on the component side of the pcb. avoid the use of vias in the decoupling circuit. series termination resistor when the pcb trace between the clock outputs and the loads are over 1 inch, series termination should be used. to series terminate a 50 ? trace (a commonly used trace impedance) place a 33 ? resistor in series with the clock line, as close to the clock output pin as possible. the nominal impedance of the clock output is 20 ? . crystal information the crystal used should be a fundamental mode (do not use third overtone), parallel resonant. crystal capacitors should be connected from pins x1 to ground and x2 to ground to optimize the initial accuracy. the value of these capacitors is given by the following equation: crystal caps (pf) = (c l - 6) x 2 in the equation, c l is the crystal load capacitance. so, for a crystal with a 16 pf load capacitance, two 20 pf capacitors should be used. if a clock input is used, drive it into x1 and leave x2 unconnected. absolute maximum ratings stresses above the ratings listed below can cause perman ent damage to the ICS650-07C. these ratings, which are standard values for idt commercially rated parts, are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for exte nded periods can affect product reliability. electrical parameters are guaranteed only over the recommended operating temperature range. recommended operation conditions item rating supply voltage, vdd 7 v all inputs and outputs -0.5 v to vdd+0.5 v ambient operating temperature (commercial) 0 to +70 c ambient operating temperature (industrial) -40 to +85 c storage temperature -65 to +150 c junction temperature 125 c soldering temperature (20 seconds max) 260 c parameter min. typ. max. units ambient operating temperature (commercial) 0 +70 c ambient operating temperature (industrial) -40 +85 c power supply voltage (measured with respect to gnd) +3.0 +3.3 +5.5 v
ICS650-07C networking clock sour ce clock synthesizer idt? / ics? networking clock source 6 ICS650-07C rev d 102709 dc electrical characteristics unless stated otherwise, vdd = 5 v ac electrical characteristics unless stated otherwise, vdd = 5 v parameter symbol conditions min. typ. max. units operating voltage vdd 3.0 5.5 v supply current idd no load 60 ma input high voltage v ih x1 pin only, clock input vdd/2+1 vdd/2 v input low voltage v il x1 pin only, clock input vdd/2 vdd/2-1 v input high voltage v ih all tri-level inputs vdd-0.5 v input low voltage v il all tri-level inputs 0.5 v input high voltage v ih other inputs, except tri-level 2v input low voltage v il other inputs, except tri-level 0.8 v output high voltage v oh i oh = -25 ma 2.4 v output high voltage v oh i oh = -8 ma vdd-0.4 v output low voltage v ol i ol = 25 ma 0.4 v short circuit current i os each output 100 ma internal pull-up resistor acs1, bcs1, oe 200 k ? parameter symbol conditions min. typ. max. units input frequency 10 12.5 or 25 27 mhz frequency error all clocks 0 ppm output rise time t or 0.8 to 2.0 v 1.5 ns output fall time t of 2.0 to 0.8 v 1.5 ns output clock duty cycle at vdd/2 40 50 60 % absolute jitter, short term variation from mean 150 ps
ICS650-07C networking clock sour ce clock synthesizer idt? / ics? networking clock source 7 ICS650-07C rev d 102709 thermal characteristics marking diagram?ics650r-07lf marking diagram?ics650r-07ilf notes: 1. ###### is the lot code. 2. yyww is the last two digits of the year, and the week number that the part was assembled. 3. ?lf? denotes pb (lead) free package. 4. ?i? denotes industrial grade device. 5. bottom marking: (origin) = country of origin if not usa. parameter symbol conditions min. typ. max. units thermal resistance junction to ambient ja still air 135 c/w ja 1 m/s air flow 93 c/w ja 3 m/s air flow 78 c/w thermal resistance junction to case jc 60 c/w 10 20 11 1 650r-07lf ###### yyww 10 20 11 1 650r-07ilf ###### yyww
ICS650-07C networking clock sour ce clock synthesizer idt? / ics? networking clock source 8 ICS650-07C rev d 102709 package outline and package dimensions (20-pin ssop, 150 mil. body) package dimensions are kept current with jedec publication no. 95 ordering information parts that are ordered with a "lf" suffix to the part nu mber are the pb-free configur ation and are rohs compliant. while the information presented herein has been checked for both ac curacy and reliability, integrat ed device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or licenses are implied. this product is intended for us e in normal commercial applications. any ot her applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommen ded without additional pr ocessing by idt. i dt reserves the right to change any circuitry or specificat ions without notice. idt does not authorize or warrant any idt product for use in life suppor t devices or critical medical instruments. part / order number marking shipping packaging package temperature 650r-07lf see page 7 tubes 20-pin ssop 0 to +70 c 650r-07lft tape and reel 20-pin ssop 0 to +70 c 650r-07ilf tubes 20-pin ssop -40 to +85 c 650r-07ilft tape and reel 20-pin ssop -40 to +85 c index area 1 2 20 d e1 e seating plane a 1 a a 2 e - c - b .10 (.004) c c l *for reference only. cont rolling dimensions in mm. millimeters inches* symbol min max min max a 1.35 1.75 0.053 0.069 a1 0.10 0.25 0.004 0.010 a2 -- 1.50 -- 0.059 b 0.20 0.30 0.008 0.012 c 0.18 0.25 0.007 0.010 d 8.55 8.75 0.337 0.344 e 5.80 6.20 0.228 0.244 e1 3.80 4.00 0.150 0.157 e .635 basic .025 basic l 0.40 1.27 0.016 0.050 0 8 0 8
? 2006 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa corporate headquarters integrated device technology, inc. www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support www.idt.com/go/clockhelp innovate with idt and accelerate your future netw orks. contact: www.idt.com ICS650-07C networking clock so urce clock synthesizer
|
